The invention relates to the field of programmable devices and to memory units adapted to be used within programmable devices. Programmable devices, such as FPGAs, typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more memory units for storage and retrieval of data used by the logic cells. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The configuration of the logic cells, functional blocks, switching circuit, and other components of the programmable device is referred to as configuration data. Configuration data can be stored in volatile or non-volatile memory on the programmable device. Additionally, configuration data can be provided and temporarily or permanently loaded into the programmable device during its manufacturing. Users specify a user design that performs a desired information processing function. Compilation software tools analyze the user design and generate corresponding configuration data that implements the desired information processing function using a programmable device. The user-created configuration data can be temporarily or permanently loaded into one or more programmable devices to implement the user design. If the user design is changed, updated configuration data can be loaded into the programmable device to implement the changed user design.
Because programmable devices are designed to implement user designs having different requirements, many of the functional blocks of programmable devices can be configured to support the needs of different types of user designs. For example, the memory units of a programmable device can be configured to support different data widths and depths. The configurable data width and depth configurations allow a memory block having a given size to be addressed and accessed in many different ways. For example, a 4 kilobit memory unit in a programmable device may be configured to operate with a 1 bit output and 4096 possible addresses; a 2 bit output and 2048 possible addresses; a 4 bit output and 1024 possible addresses; a 8 bit output and 512 possible addresses; a 16 bit output and 256 possible addresses; or a 32 bit output and 128 possible addresses.
To provide configurable memory access width and depth, memory units in programmable devices typically include width encoding and decoding logic for writing and reading data to and from memory units. For example, width decoding logic can be placed between read sense amplifiers and the output of the memory unit to redirect data to the appropriate data output line based upon the data width specified for the memory unit. In this implementation, the memory read access time (Tco) includes not only delay contributions from normal reading mechanisms, such as address decoding, bit-lines precharge or discharge, and sense amplifier operation, but also a time delay from the width decoding logic. Often, the width decoding logic introduces a substantial time delay due to its large fan-out and capacitive loading. For user designs requiring high speed memory access, the extra time delay introduced by the width decoding logic can be unacceptable. Moreover, many high frequency user designs do not require memory units with configurable data widths, instead preferring to access memory units using their full data widths.
It is therefore desirable for a programmable device to include memory units that provide improved access times for full data width access despite the presence of width decoding logic. It is further desirable for the programmable device to enable more complicated width decoding schemes that do not compromise access times. It is also desirable for memory units to provide improved access times for full data width access without requiring substantial additional complexity.